The present invention relates to the field of integrated circuit memories, specifically, to a method and apparatus for conserving power in a pre-charge high read-only memory (ROM) array.
Read-only memory (ROM) is non-volatile memory that may be read but not written to. In a conventional ROM array, memory cells are arrayed in rows and columns. Each memory cell is associated with one row line and one column line. Just prior to reading one or more memory cells in the array, all column lines in the array are typically pre-charged high; that is, a voltage corresponding to a logical 1 is provided to the column lines.
FIG. 1 shows a slice 10 of a ROM array according to the prior art. For a ROM array with a word length W, slice 10 of FIG. 1 would be repeated W times. For example, for an 8-bit word length, the ROM array would include eight slices such as slice 10, including eight N-to-1 multiplexers 200 that each output the value of one bit of the 8-bit word onto a bit output such as bit output 210 of FIG. 1.
Memory cells C11 through CMN are associated with row lines 50-1 through 50-M and column lines 60-1 through 60-N. For example, memory cell C11 is associated with row line 50-1 and column line 60-1. During the fabrication of slice 10, memory cells C11 through CMN are programmed to output a logical 1 or a logical 0. The content of a memory cell may be read by providing signals to its associated row lines and column lines.
In order to read one of the memory cells such as cell C11, column lines 60-1 through 60-N are first pre-charged high. In order to pre-charge the column lines, a pre-charge signal is asserted low to the gate of PFET pull-up transistors 100-1 through 100-N, turning on the transistors. A voltage supply, VDD, coupled to the source of transistors 100-1 through 100-N, pre-charges each selected column line to a pre-charge voltage corresponding to a logical 1 through the connection to the drain of the transistor. The pre-charge voltage may be approximately 3.3 volts. The transistors 100-1 through 100-N are then turned off by asserting the pre-charge signal high. The column lines remain charged high, but are no longer connected to source voltage supply VDD.
Next, a voltage corresponding to a logical 1 is applied to one of the row lines 50-1 through 50-M. For example, if the bit stored in memory cell C11 is part of the word being read, a voltage is applied to row line 50-1 after column lines 60-1 through 60-N have been pre-charged high. If cell C11 has been programmed to output a logical 0, the voltage of the column line 60-1 is discharged. On the other hand, if cell C11 has been programmed to output a logical 1, the voltage of column line 60-1 is not discharged. The output of column lines 60-1 through 60-N are input to N to 1 multiplexer 200. Multiplexer 200 outputs a voltage corresponding to the value of the chosen cell on bit output 210.
One drawback to the prior art system is that all column lines in the ROM array are pre-charged, regardless of the length of the word to be read. For battery-operated and other power-sensitive devices, pre-charging all column lines is not efficient.
Therefore, it is desirable to provide a read-only memory system and method of using the system that does not require pre-charging all column lines.
In order to conserve power in a ROM array using a pre-charge high, pull-down low scheme, switches are placed between the pre-charge high stage and the memory array. Therefore, for a word of length W, only W column lines are pre-charged, rather than all of the column lines in the ROM array.
According to an embodiment of the invention, a read-only memory system includes a ROM array with memory cells arranged in multiple columns and multiple rows. The ROM array includes a plurality of memory cells, each of which is programmed with one bit of data. For example, a memory cell may be programmed as a logical 1 or a logical 0. Each memory cell is associated with one column line and one row line so that its content may be read.
The read-only memory system includes a switching mechanism for each column line in the memory array, and an address system. The switch couples or decouples a first portion of the column line coupled memory cells in the array and a second portion of the column line coupled to a pre-charge voltage supply. For simplicity, the first portion of the column line may be referred to as the column line, while the second portion of the column line may be referred to as the pre-charge line. The address system includes an address bus to provide address information to address gates associated with the column lines. A signal from an address gate closes its corresponding switch, coupling the selected column line to its pre-charge line and subsequently pre-charging the column line. According to an embodiment, the switching mechanism is a full transmission gate, although other types of switches are also suitable. A high signal from the address gate turns on the full transmission gate, coupling the column line to its associated pre-charge line. A pre-charge voltage is then coupled to each selected column line through the corresponding pre-charge lines. If the input of the full transmission gate is not high, the column line is de-coupled from its associated pre-charge line and therefore is not coupled to the pre-charge voltage.
The read-only memory system includes a pre-charge system for providing a pre-charge voltage to selected column lines through associated pre-charge lines. The pre-charge system includes a pull-up transistor, whose source is connected to a source voltage supply. When the pull-up transistor is turned on, the pre-charge line is coupled to the voltage supply through the drain of the pull-up transistor. When the switch couples the pre-charge line to its associated column line, the column line is pre-charged by the source voltage supply.
The read-only memory system includes one or more multiplexers. The input terminals of each multiplexer are connected to the pre-charge lines associated with each of the column lines. Each multiplexer has one or more output terminals. When a word of data is being read, each output corresponds to the value of one of the bits comprising the word. According to an embodiment of the invention, there are W multiplexers to read a word of length W. Each multiplexer has a plurality of input terminals, and each multiplexer outputs one bit of the word. The multiplexer may be a simple AND gate, where the inputs corresponding to the column lines that are not associated with a bit in the word to be read are high, while the input corresponding to the column line that is associated with a bit to be read is high if the bit is a 1 and low if the bit is a 0.
According to an embodiment of the invention, a read operation may be performed using a memory system as described above. In order to read a word of length W, an address bus first sends a signal to each of the W address gates corresponding to the W column lines associated with a bit to be read. The output of the address gates is input to the corresponding switching mechanism, coupling the column line to its associated pre-charge line only when the column line includes a bit to be read. According to an embodiment of the invention, the address gates are AND gates, and the inputs of the AND gate are both high to select the corresponding column line for precharging. The column line is selected by providing the address gate output to the input of the full transmission gate, which acts as a closed switch when its input is high. The selected column line is thereby connected to the pre-charge voltage through the pre-charge line when the input of the full transmission gate is high.
After the full transmission gate connects each selected column line to the associated pre-charge line, a pre-charge signal is provided, coupling the selected column lines to a pre-charge voltage supply. The pre-charge signal is then turned off, leaving the column lines at the pre-charge voltage but de-coupling the column lines from the pre-charge voltage supply. In an embodiment of the invention, a voltage supply VDD provides a voltage to the source of the pull-up transistor. A pre-charge signal is provided to the gate of the pull-up transistor, turning it on and pre-charging selected column lines through their corresponding pre-charge lines, which are coupled to the drain of the transistor. After the selected column lines are pre-charged, the pre-charge signal is turned off. The selected column lines remain coupled to the drain of the pull-up transistor through the pre-charge line, but are no longer connected to the source voltage supply.
Next, a voltage is applied to selected row lines, corresponding to memory cells whose content is to be read. The voltage of the associated column lines containing a memory cell that is programmed as a logical 1 remains high. However, the voltage of the associated column lines containing a memory cell that is programmed as a logical 0 is discharged.
The voltage of each selected column line is detected, in order to read the value of each bit in the word. According to an embodiment of the invention, the voltage of each selected column line is coupled to an input terminal of a multiplexer through its associated pre-charge line. The multiplexer output corresponds to the value of one or more bits in the word being read. Multiple multiplexers may be used, where each outputs less than W bits of the word.